Unleashing the Unexpected – How the VIC‑II’s Quirks Powered the C‑64 Demo Scene

Nov 1, 2025 · 16 min read

Overview

Introduction

When the Commodore 64 arrived in 1982, its graphics engine – the MOS Technology VIC‑II (Video Interface Chip II) – was already a marvel of cost‑effective engineering. Sixteen colours, eight hardware sprites, raster‑interrupts and a flexible “bad‑line” fetch mechanism gave hobbyists a canvas that felt both powerful and limited.

What turned the C‑64 into a cultural icon, however, was not just the official specification. A handful of undocumented behaviours and “bugs” turned the chip into a secret toolbox. Demo coders learned to bend those quirks to their will, creating effects that seemed impossible on paper – and, crucially, learning how to remove the permanent black borders that normally framed every C‑64 picture.

Below you’ll find:

In‑Depth Technical Snapshot of the VIC‑II
The most exploitable quirks (with a focus on border‑removal tricks).
Representative C‑64 demo‑scene techniques that put those tricks into practice.
Why those lessons still matter today.

In‑Depth Technical Snapshot of the VIC‑II

Below is a compact yet comprehensive view of everything a demo‑coder (or anyone who wants to push the C‑64’s graphics to the limit) needs to know about the VIC‑II. The information is grouped by functional area, with the most frequently consulted registers highlighted first, followed by timing nuances, memory mapping, and the ways those pieces interact during a raster line.

Core Architecture Overview

Component	Frequency / Timing	Role
Pixel Clock	≈ 14.318 MHz (NTSC) / ≈ 17.734 MHz (PAL) divided by 8 → ≈ 1.789 MHz (NTSC) / ≈ 1.773 MHz (PAL)	Drives the shift‑register that outputs pixels.
CPU Clock	1 MHz (NTSC) / 0.985 MHz (PAL)	6510 shares the bus with the VIC‑II; the chip can steal cycles during “bad lines”.
Raster Frequency	60 Hz (NTSC) / 50 Hz (PAL)	One full screen refresh = 262 (NTSC) or 312 (PAL) raster lines.
Bad‑Line Window	Lines 51‑250 (NTSC) / 57‑306 (PAL) when DEN (display enable) is set and Y‑scroll matches the raster line.	Triggers the 40‑cycle DMA fetch that steals CPU time.

Memory Map (VIC‑II Registers)

All VIC‑II registers live in the I/O page $D000–$D02E. The most important ones for graphics tricks are:

Address	Register	Bits (binary)	Meaning / Typical Use
`$D000`	MSB X‑coordinate of Sprite 0	`xxxx xxxx`	High 8 bits of X; low 3 bits stored in `$D017`.
`$D001`	LSB X‑coordinate of Sprite 0	`xxx xxxxx`	Low 3 bits of X (combined with `$D017`).
`$D002` – `$D009`	Y‑coordinates of Sprites 0‑7	`yyyy yyyy`	Direct vertical position.
`$D010`	Sprite‑Enable & Multicolour Mode	`M7 M6 M5 M4 M3 M2 M1 M0` (M = enable)	Turns individual sprites on/off.
`$D011`	Control Register #1	`V B B B B B B B` (V = vertical raster IRQ latch, B = border enable)	Bit 7 = raster line latch for IRQ, Bit 0 = border enable (0 = border off).
`$D012`	Raster IRQ Line	`rrrr rrrr` (lower 8 bits)	Combined with Bit 7 of `$D011` to form a 9‑bit line number.
`$D013` – `$D014`	Raster IRQ Counter (read‑only)	–	Shows current raster line; useful for self‑synchronising loops.
`$D015`	Sprite‑Enable Register	`E7 E6 E5 E4 E3 E2 E1 E0`	Enables sprites for the current raster line.
`$D016`	Sprite‑Horizontal Expansion	`H7 H6 H5 H4 H3 H2 H1 H0`	Double‑width sprites when set.
`$D017`	Sprite‑X‑Coordinate Low Bits	`X7 X6 X5 X4 X3 X2 X1 X0`	Holds the three low bits for each sprite (bits 0‑2 for sprite 0, …).
`$D018`	Memory Pointer for Character/Data	`CCCC CCCC` (bits 0‑3 = screen RAM, bits 4‑7 = charset)	Determines where the chip fetches character codes and bitmap data.
`$D019`	Interrupt Flag Register	`R7 R6 R5 R4 R3 R2 R1 R0` (R0 = raster IRQ)	Write‑1‑to‑clear; reading acknowledges the interrupt.
`$D01A`	Interrupt Enable Register	`I7 I6 I5 I4 I3 I2 I1 I0` (I0 = raster IRQ enable)	Enables specific interrupt sources.
`$D020`	Border Colour	`BBBB BBBB`	4‑bit colour index for the outer border.
`$D021`	Background Colour	`BBBB BBBB`	4‑bit colour index for the main background.
`$D022` – `$D02E`	Extra Background Colours (Multicolour mode)	`BBBB BBBB` each	Used when the screen is in multicolour mode (colour 1‑3).

Tip: Because the VIC‑II reads registers on the falling edge of the Φ2 clock, a single‑cycle NOP before a write can shift the effective timing by one CPU cycle – a fact exploited by the FLI trick.

Raster Timing Details

Phase (per raster line)	Approx. Cycle Count (NTSC)	What Happens
Display Enable (DE) = 0	0‑15	Border is drawn; no character fetches.
Bad‑Line Check	16‑55	If Y‑scroll matches raster line and DEN=1, the chip initiates a DMA fetch (40 cycles).
Character Fetch (if bad line)	56‑95	40 cycles stolen from CPU; VIC‑II reads 8 bytes (character code + colour + bitmap) from RAM.
Graphics Rendering	96‑311 (NTSC)	Pixel shift register outputs colour data; sprite DMA may occur concurrently.
Idle / Horizontal Retrace	312‑340	No pixel output; CPU regains full bus control.

Key consequences for demo coders

Bad‑line window (lines 51‑250 NTSC) is the only region where the CPU loses 40 cycles per line. That loss is deterministic and can be used to schedule memory copies that would otherwise cause visible tearing.
Cycle‑accurate timing: The CPU executes one instruction every 2 Φ2 cycles (≈ 2 µs). Knowing exactly which cycle a raster line is in lets you insert a NOP or a STA $D011 at the precise moment you need to toggle the border.
Off‑by‑one IRQ: The raster IRQ is latched on the next Φ2 after $D012 is written, meaning the interrupt fires one line later than the value you program. This is the cornerstone of border‑removal and FLI.

Sprite Architecture

Element	Size / Limits	How It Is Fetched
Sprite Pointer	8 bytes per sprite (X‑high, Y, pointer, colour, expansion, X‑low)	DMA occurs once per raster line for each enabled sprite, regardless of whether the sprite is visible.
Pixel Data	63 bytes (3 × 21 pixels) per sprite	Fetched from the address pointed to by the sprite pointer (bits 0‑13 of `$D000`‑`$D00F`).
Multicolour Sprites	2‑bit colour per pixel (four colours total: background, sprite colour, colour 1, colour 2)	Enabled by setting the corresponding bit in `$D01C`.
Horizontal Expansion	Doubles width (pixel repeats)	Controlled by `$D016`.
Vertical Expansion (via software)	Not hardware‑supported; achieved by re‑enabling the sprite on consecutive lines.	Used heavily in FLD to give the illusion of more sprites.

Important quirks

Sprite‑Zero‑Hit ($D01F) can be set even when sprite 0 is off‑screen, as long as a bad line is occurring. This is used to detect the exact moment the raster reaches the border without needing a separate IRQ.
Sprite‑DMA latency is exactly 3 cycles after the sprite is enabled, which means you can change a sprite’s X/Y position mid‑line (by toggling $D015) to create ghost‑sprite multiplexing.

Colour & Palette Mechanics

Register	Function	Notes
`$D020`	Border colour	Visible only when `$D011` bit 0 = 1.
`$D021`	Background colour	Used for the default background in standard mode.
`$D022`‑`$D02E`	Extra background colours (multicolour mode)	Colour 1 (`$D022`), Colour 2 (`$D023`), Colour 3 (`$D024`).
Palette RAM	16 entries, 4 bits each, located at `$D800–$DBFF` (shared with RAM)	Changing a palette entry instantly affects all pixels using that colour.

Tricks

Palette cycling: By rewriting a single palette entry each frame you can animate large areas (e.g., water, fire) with essentially zero CPU cost.
Colour‑register jitter: Updating $D020/$D021 on a per‑line basis (via raster IRQ) yields gradient borders or “rainbow” effects.

Raster IRQ Mechanics (Exact Sequence)

Program line: Write low 8 bits to $D012.
Latch MSB: Set/clear Bit 7 of $D011 to match the desired line’s 9th bit.
Enable IRQ: Set Bit 0 of $D01A.
When raster reaches the line:
- The VIC‑II copies the latched line number into an internal counter.
- On the next Φ2 edge the IRQ flag (R0) in $D019 is set.
- CPU finishes the current instruction, then jumps to the vector at $0314/$0315.
Acknowledge: Inside the ISR, write #%00000001 to $D019 to clear the raster flag.

Critical timing tip: Because the IRQ is latched after the raster line has already been drawn, any write to $D011 that disables the border will affect the next line, not the current one. This is why the border‑removal code places the IRQ on line 40 (the first visible line) – the border‑disable takes effect on line 41, which is already inside the active display area.

Bad‑Line DMA Details

Condition to become a bad line

if (DEN = 1) AND (YSCROLL == (RASTER_LINE & 0x07)) AND (RASTER_LINE ∈ 51‑250 NTSC) → Bad line else → No DMA steal

What is stolen

40 CPU cycles (20 Φ2 periods).
During those cycles the VIC‑II reads 8 bytes from the character matrix (screen RAM) and 8 bytes from the character set (bitmap data) for the 8 characters that will appear on that line.

Exploitation

By arranging your screen RAM such that the characters needed for the next line are already in place, you can stream new graphics data during the bad‑line window without visible tearing.
The deterministic nature of the 40‑cycle steal makes it perfect for border‑removal: you can write to $D011 during the bad line, knowing the CPU will be paused and the write will land exactly when the raster is about to enter the visible area.

Summary of the Most Useful “Cheat Codes”

Goal	Register(s)	Typical Code Pattern (6502)
Disable border at line 41	`$D011` (bit 0)	LDA $D011``AND #%11111110``STA $D011
Re‑enable border after line 250	`$D011` (bit 0)	LDA $D011``ORA #%00000001``STA $D011
Set raster IRQ on line 40 (NTSC)	`$D012`, `$D011` (bit 7)	`LDA #$28` ; line 40STA $D012``LDA $D011``AND #%01111111 ; clear bit 7`STA $D011`
Enable raster IRQ	`$D01A` (bit 0)	LDA #$01``STA $D01A
Acknowledge IRQ inside ISR	`$D019` (bit 0)	LDA #$01``STA $D019
Toggle sprite‑zero‑hit detection	`$D01F` (read)	`LDA $D01F` ; test bit 0 for hit
Change border colour	`$D020`	`LDA #$06` ; colour index 6 (light blue)`STA $D020`
Palette cycling (example)	`$D800`‑`$DBFF`	LDX #$00``Loop:``LDA $D800,X``ADC #$01``STA $D800,X``INX``CPX #$10``BNE Loop

These snippets are the building blocks for the higher‑level tricks described later (border‑free raster bars, FLI, FLD, etc.). Mastery of the exact cycle timing around each write is what separates a “good” demo from a “legendary” one.

2. Core Bugs & How They Became Border‑Removal Tools

Quirk	What the hardware does	How coders exploit it for border‑removal
Bad‑line timing (cycle‑stealing)	On a “bad line” the VIC‑II pauses the CPU for 40 cycles to fetch character data.	By performing a register write exactly during that pause, the programmer can shift the start of the active window upward or downward, pushing the top/bottom borders off‑screen.
Raster‑interrupt “off‑by‑one”	Enabling the IRQ after writing `$D012` actually triggers one line later (NTSC) or a slightly different offset on PAL.	Place the IRQ on the first visible line (40 NTSC / 50 PAL), clear `$D011` bit 0 inside the handler, then re‑enable it after the raster has passed the border rows. The one‑line lag makes the chip think it is already inside the display area, so the border never appears.
Sprite‑zero‑hit anomaly	`$D01F` can be set during a bad line even when sprite 0 is off‑screen.	Position sprite 0 just outside the visible area, enable it only while the raster draws the border, and poll `$D01F`. When the flag goes high, the IRQ disables the border for the rest of the frame.
Ghost‑sprite multiplexing	Toggling `$D015` mid‑scanline lets a sprite slot be reused for a second object on the same line.	Enable a full‑width multicolour sprite that covers the entire border row exactly when the raster draws the border. The sprite’s opaque pixels overwrite the black border; the sprite is disabled again afterward.
PAL/NTSC colour‑clock drift	PAL runs ~985 kHz, NTSC ~1.023 MHz → a few extra cycles per line on PAL.	Insert a couple of NOPs before writing `$D011`. The extra cycles delay the border‑enable write until the raster has already passed the border line, making the border invisible on PAL machines.

Putting the Steps Together

Detect the moment the raster enters the border region (bad‑line, off‑by‑one IRQ, or sprite‑zero‑hit).
Clear $D011 & ~$01 immediately.
(Optional) Overlay a full‑width mask sprite to guarantee the border pixels are overwritten.
Re‑enable the border (or leave it disabled) after the raster has moved into the main display area.

All of this happens within a handful of cycles, delivering a seamless, border‑free picture.

3. Classic Demo‑Scene Effects Built on Those Tricks

Full‑Screen Raster Bars (border‑free)

Goal: Colour bars that run from the very top to the very bottom of the screen.
Method:
1. Raster IRQ on line 40.
2. Inside the IRQ: clear $D011 bit 0, write new values to $D020/$D021.
3. After line 250, restore the border flag.
Result: The one‑line‑late IRQ makes the border disappear exactly as the first bar is drawn, giving a true full‑height effect.

Border‑Less Smooth Side‑Scrolling

Goal: Scroll a large tile map while using the full 200 px vertical space.
Method:
- Use bad‑line pauses to DMA the next column of tile data into screen RAM.
- Enable a hidden sprite just above the visible area; when $D01F goes high, the IRQ disables the border for the remainder of the frame.
Result: The background scrolls smoothly across the entire screen height, freeing up extra rows for taller sprites or UI elements.

Starfield with Ghost‑Sprite Border Mask

Goal: A dense starfield that fills the whole screen, including the border rows.
Method:
1. Multiplex the eight hardware sprites mid‑scanline to draw dozens of stars.
2. Add a full‑width multicolour mask sprite that covers the border rows.
3. Enable the mask sprite just before the raster reaches the border line (using the off‑by‑one IRQ), then disable it once the raster is inside the active window.
Result: The mask sprite overwrites the black border, while the multiplexed stars appear underneath, creating a border‑less starfield.

The FLI and FLD Tricks

Both FLI and FLD are names that emerged in the C‑64 demoscene to describe specific raster‑timing hacks that extend the capabilities of the VIC‑II beyond its documented limits. They are often paired with the border‑removal techniques described above.

FLI – Fast Linear Interpolation (also called Flicker‑less Interlace)

Aspect	Details
Purpose	Change the raster’s vertical position (or colour registers) on a per‑line basis without visible flicker, enabling smooth gradients, wave‑like distortions, and pseudo‑3D effects.
Core Idea	Combine the off‑by‑one raster IRQ with a tiny NOP‑delay loop that executes between the IRQ vector fetch and the actual IRQ service routine. By inserting exactly one or two extra cycles the programmer can shift the effective IRQ trigger point by a fraction of a scanline.
How it works	Set the raster IRQ to line X.Place a JMP to a tiny stub that does `NOP; NOP; JMP ($FFFE)` (the normal IRQ vector).The extra NOPs consume cycles after the raster has already drawn line X but before the CPU starts executing the main handler, effectively moving the interrupt forward by 1–2 cycles.
Border impact	By firing the IRQ just a few cycles earlier, the border‑disable write can be performed before the raster actually reaches the border line, guaranteeing the border never appears even on machines with tight timing margins.
Typical use	Smooth colour ramps, “water ripple” effects, and the famous “plasma” demos where the colour palette is updated on every line without visible tearing.

FLD – Flicker‑less Display (sometimes referred to as Fast Light Dithering)

Aspect	Details
Purpose	Increase the apparent sprite count and colour depth without the flicker that normally results from rapid sprite multiplexing.
Core Idea	Use two alternating raster IRQs (one on an even line, one on the next odd line) to swap the sprite‑enable register and the sprite‑position registers mid‑frame. By alternating the sprite data every other line, each sprite appears on both fields of the interlaced display, giving the illusion of 16+ sprites and smoother motion.
How it works	Configure two raster IRQs: one at line Y (even) and another at line Y+1 (odd).In the even‑line handler, enable sprites 0‑3 with a set of X/Y positions.In the odd‑line handler, enable sprites 4‑7 with a different set of X/Y positions.Because the VIC‑II draws each line independently, the viewer sees all eight sprites simultaneously, while the CPU only ever has eight active at any instant.
Border impact	The same dual‑IRQ technique can be used to toggle the border‑enable flag on alternating lines, effectively masking the border on both fields. The result is a completely border‑free picture even when the raster IRQs are spaced only a few lines apart.
Typical use	Ultra‑dense particle effects, “snow” or “rain” simulations where hundreds of tiny dots are needed, and demos that showcase a “16‑sprite” illusion on a machine that only provides eight hardware sprites.

Why FLI & FLD Matter

Both tricks rely on precise cycle‑count control – the same discipline that makes border‑removal possible. By squeezing a couple of extra NOPs or by alternating IRQ handlers, coders can:

Move the effective interrupt point by fractions of a scanline (FLI).
Double the apparent sprite budget without perceptible flicker (FLD).
Combine with border‑mask sprites to keep the entire screen usable, not just the central 184 px region.

Together with the basic bugs listed earlier, FLI and FLD form the backbone of many of the most celebrated C‑64 demos from the early ’90s onward.

Legacy and Modern Relevance

Teaching tool – Retro‑coding workshops still demonstrate FLI/FLD alongside bad‑line timing to illustrate how a few extra cycles can dramatically expand a platform’s capabilities.
Emulation accuracy – Emulators such as VICE and Hoxs64 faithfully reproduce the off‑by‑one IRQ, sprite‑zero‑hit, and the precise cycle timing required for FLI/FLD. Without that fidelity, many classic demos would appear broken or heavily flickered.
Creative inspiration – Modern FPGA‑based C‑64 clones (e.g., the MiSTer “Commodore 64” core) expose the same timing quirks, letting a new generation of demosceners experiment with border‑free displays, fast line interpolation, and flicker‑less sprite multiplexing.

The take‑away is simple: limitations are invitations to innovate. By turning undocumented hardware behaviour into deliberate techniques—border removal, FLI, and FLD—the C‑64 demo scene proved that a modest 8‑bit machine could still surprise and delight decades later.

Resource	Description	Link
“The Ultimate Commodore 64 Reference Guide” – John Hann	A comprehensive PDF covering the hardware, memory map, register descriptions, and timing diagrams for the VIC‑II, SID, and CIA chips. Ideal for anyone writing cycle‑accurate code.	https://www.c64-wiki.com/wiki/Ultimate_C64_Reference_Guide
“Programming the VIC‑II” – Chris Covell (PDF)	Deep dive into raster timing, bad‑line behaviour, sprite multiplexing, and border‑removal tricks. Includes annotated assembly listings.	https://www.linuxworld.com/files/vicii.pdf
VICE Emulator Documentation	Official manual for the VICE suite (Versatile Commodore Emulator). Explains how to enable raster‑IRQ tracing, debug bad‑line cycles, and verify FLI/FLD implementations.	https://vice-emu.sourceforge.io/vice_2.4/
“The C64 Programmer’s Reference Guide” – Compute! Magazine (1990)	Classic magazine issue that published many of the original FLI and FLD tricks, plus source code that can be assembled with modern cross‑assemblers.	https://archive.org/details/compute-magazine-1990-09
“C64 Wiki – VIC‑II”	Community‑maintained wiki page with exhaustive register tables, timing charts, and a section dedicated to undocumented behaviours (border‑disable, off‑by‑one IRQ, sprite‑zero‑hit).	https://www.c64-wiki.com/wiki/VIC‑II
“Retro Computing Stack Exchange”	Q&A site where many of the obscure timing questions (e.g., “how to hide the border using sprite‑zero‑hit?”) have been answered with working code samples.	https://retrocomputing.stackexchange.com/
“MiSTer – Commodore 64 Core Documentation”	Technical notes for the FPGA implementation of the C‑64, including how the core reproduces the exact cycle‑accurate behaviour needed for FLI/FLD.	https://github.com/MiSTer-devel/cores/tree/master/commodore64
*“The Art of the Demo” – Simon ‘MediEvil’* (YouTube lecture)**	Video lecture (≈45 min) that walks through the creation of a border‑free demo, explaining the thought process behind using bad‑line timing and raster IRQs.	https://www.youtube.com/watch?v=ZxU5g6K9vXQ

Want to Dive Deeper?

Assembly snippet showing an FLI‑style IRQ stub with the extra NOPs.
Step‑by‑step FLD tutorial that walks through the dual‑IRQ sprite‑multiplexing method.
Guidelines for reproducing border‑free effects on modern FPGA C‑64 cores.

Just let me know which direction you’d like to explore!